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1CY M74 S55 0, CYM7 4S 551
PRELIMINARY
CYM74B550 CYM74P550A CYM74S550, CYM74S551
OPTi Viper Chip Set Level II Cache Module Family
Features
* Pin-compatible secondary cache module family * Asynchronous (CYM74B550), synchronous pipelined (CYM74P550A), or synchronous burst (CYM74S550, CYM74S551) modules * Ideal for Intel P54C/P55C systems with the OPTi Viper chipset * Operates at 50, 60, and 66 MHz * Uses cost-effective CMOS asynchronous SRAMs or high-performance synchronous SRAMs * 160-position Burndy DIMM CELP2X80SC3Z48 connector * 3.3V inputs/ data outputs volt SRAMs and 3.3 volt level translators. These modules offer 3-2-2-2 performance at CPU bus speeds up to 66 MHz. The synchronous modules are available with low cost synchronous pipelined RAMs or high performance synchronous burst RAMs. The CYM74P550A is a high performance synchronous pipelined burst 256 KB module and is based on industry standard 32Kx32 pipelined BSRAM. The CYM74P550A has series damping resistors on the data lines. The CYM74S550 and CYM74S551 are high performance synchronous burst cache modules that provide 256-Kbytes and 512-Kbytes of cache respectively. These modules support 3-1-1-1 performance at 66 MHz. All of these modules include storage for 8-bits of tag and one dirty bit. Multiple ground pins and on-board decoupling capacitors ensure high performance with maximum noise immunity. All components on the cache modules are surface mounted on a multi-layer epoxy laminate (FR-4) substrate. The contact pins are plated with 100 micro-inches of nickel covered by 10 micro-inches of gold flash.
Functional Description
This family of secondary cache modules is designed for Intel P54C/P55C systems with the OPTi Viper chip set. CYM74B550 is a low cost asynchronous cache module that provides 256-Kbytes of cache with industry standard 32Kx8 5
Logic Block Diagram - CYM74B550
TAGWE 16Kx1 DIRTYWE DIRTYI WE DQ A 13:0 A17 -A5 2X 373C HACALE OCA 4 ECA 4 ECAWE ECDOE CS7-CS 0 LE LA 17-LA5 A14:2 A1 A0 WE OE CE CS 7 CE CS 6 CE CS 5 VCC 7X CYBUS3384 CD63 -CD0 A B BE 2 GND BE 1
74b550-1
8Kx8 WE D A 13:0 A17 -A 5
CYM74B550
PD 3 NC
PD 2 NC
PD 1 GND
PD 0 GND
TAG 7 -TAG 0
A17 -A 5 LA 17 -LA 5 32Kx 8
DIRTYO 5V only SRAMs D CD 63-CD 0
CE CS 4
CE CS 3
CE CS 2 VCC5
CE CS 1
CE
LSB CS 0
100 ohms 4.3V zener 5% tolerance
GND
D 63 -D0 module 3.3V compliant databus
Intel is a trademark of Intel Corporation.
OPTi is a trademark of OPTi, Inc.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 July 1995 - Revised October 1996
PRELIMINARY
CYM74B550 CYM74P550A CYM74S550, CYM74S551
Logic Block Diagram - CYM74P550A
TAGWE 16Kx1 DIRTYWE DIRTYI WE D Q 8Kx8 (CYM74P550A) WE D A13:0 A17 -A 5 DIRTYO D63-D0 CLK CK D A17 -A 3 WE 7-WE 0 ADSP ADSC ADV SYNCS 0 ECDOE A
15
PD3 CYM74P550A NC
PD 2 NC
PD 1 GND
PD0 NC
TAG 7 - TAG 0
A13:0 A17 -A 5
CK D 63-D 32 A WE 3-WE 0 BE 3-BE0 ADSP ADSC ADV CE1 OE VCC3 CE 2 VSS CE 3
32Kx32 74b550-2
D
D 31-D 0
WE 7-WE 4
BE 3 -BE0 ADSP ADSC ADV CE1 OE
VCC3 CE 2 VSS CE 3
32Kx32
2
PRELIMINARY
Logic Block Diagram - CYM74S550, CYM74S551
TAGWE 16Kx1 DIRTYWE DIRTYI WE D Q 8Kx8 (CYM74S550) 32Kx8 (CYM74S551) WE D A13:0 A18-A 5
CYM74B550 CYM74P550A CYM74S550, CYM74S551
Note: A18 is not used by CYM74S550 PD3 NC NC PD2 NC GND PD1 NC NC PD0 GND GND
CYM74S550 CYM74S551 TAG 7-TAG 0
A13:0 A18-A 5
DIRTYO 32Kx18(CYM74S550) 64Kx18(CYM74S551) A18-A 3 ADSP ADSC ADV SYNCS 0 ECDOE CLK MSB WE7-WE 0 A15:0 ADSP ADSC ADV CE OE CLK WE 1:0 WE 7:6 WE 1:0 WE 5:4 WE 1:0 WE 3:2 WE 1:0 LSB WE 1:0
74b550-3
D
D63-D 0
DP
Pullup to VCC3
Selection Guide
Asynchronous Cache Modules Part Number Cache Size System Clock Data SRAM tAA Tag SRAM tAA 50 MHz 25 ns 20 ns 74B550-50 74B550-60 256 KB 60 MHz 15 ns 15 ns Synchronous Pipelined Cache Modules Part Number Cache Size System Clock Data SRAM tCO Tag SRAM tAA 50 MHz 12 ns 20 ns 74P550A-50 74P550A-60 256 KB 60 MHz 9 ns 15 ns Synchronous Burst Cache Modules Part Number Cache Size System Clock Data SRAM tCO Tag SRAM tAA 50 MHz 12 ns 20 ns 74S550-50 74S550-60 256 KB 60 MHz 9 ns 15 ns 66 MHz 9 ns 12 ns 50 MHz 12 ns 20 ns 74S550-66 74S551-50 74S551-60 512 KB 60 MHz 9 ns 15 ns 66 MHz 9 ns 12 ns 74S551-66 66 MHz 9 ns 12 ns 74P550A-66 66 MHz 15 ns 12 ns 74B550-66
3
PRELIMINARY
Pin Configuration
CYM74B550 CYM74P550A CYM74S550, CYM74S551
Dual Read-Out SIMM (DIMM) Top View
GND D63 D61 VCC5 D59 D57 D55 GND D53 D51 D49 VCC5 D47 D45 GND D43 D41 D39 D37 GND D35 D33 D31 D29 GND D27 D25 VCC5 D23 D21 D19 GND D17 D15 D13 GND D11 VCC5 D9 D7 GND D5 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GND D62 D60 NC (74B550) / VCC3 (74P550A, 74S55X) D58 D56 D54 GND D52 D50 D48 NC (74B550) / VCC3 (74P550A, 74S55X) D46 D44 GND D42 D40 D38 D36 GND D34 D32 D30 D28 GND D26 D24 NC (74B550) / VCC3 (74P550A, 74S55X) D22 D20 D18 GND D16 D14 D12 GND D10 NC (74B550) / VCC3 (74P550A, 74S55X) D8 D6 GND D4 NC (74B550) / VCC3 (74P550A, 74S55X) D2 D0 NC (74B550) / VCC3 (74P550A, 74S55X) OCA4 (74B550) / ADV(74P550A, 74S55X) OCAWE(74B550) / SYNCS1 (74P550A, 74S55X) OCDOE CS 1 (74B550) / WE1 (74P550A, 74S55X) GND CS 3 (74B550) / WE3 (74P550A, 74S55X) CS 5 (74B550) / WE5 (74P550A, 74S55X) NC (74B550) / VCC3 (74P550A, 74S55X) CS 7 (74B550) / WE7 (74P550A, 74S55X) HACALE (74B550) / ADSP(74P550A, 74S55X) GND TAGWE NC (74B550) / A4 (74P550A, 74S55X) A6 A8 GND A10 A12 A14 NC (74B550) / VCC3 (74P550A, 74S55X) A16 A18 NC (Reserved A20) GND DIRTY O TAG 1 NC (74B550) / VCC3 (74P550A, 74S55X) TAG 3 TAG 5 GND TAG 7 PD1 PD3 NC (74B550) / VCC3 (74P550A, 74S55X) 74b550-4
VCC5 D3 D1 VCC5 (74P550A, 74S55X) ADSC / (74B550) ECA4 (74P550A, 74S55X) SYNCS0 / (74B550) ECAWE ECDOE (74P550A, 74S55X) WE0 / (74B550) CS 0 GND (74P550A, 74S55X) WE2 / (74B550) CS 2 (74P550A, 74S55X) WE4 / (74B550) CS 4 VCC5 (74P550A, 74S55X) WE6 / (74B550) CS 6 (74P550A, 74S55X) CLK / (74B550) NC GND DIRTYWE (74P550A, 74S55X) A3 / (74B550) NC A5 A7 GND A9 A11 A13 VCC5 A15 A17 (Reserved A19) NC GND DIRTYI TAG 0 VCC5 TAG 2 TAG 4 GND TAG 6 PD0 PD2 VCC5
4
PRELIMINARY
Pin Definitions
Common Signals VCC5 VCC3 GND A18-A5 D63-D0 ECDOE TAG7-TAG0 TAGWE DIRTYI DIRTYO DIRTYWE PD3-PD0 NC CYM74B550 Only Signals HACALE OCA4 ECA4 CS7-CS0 ECAWE CYM74P550A,CYM74S55X Signals CLK A4-A3 ADSC ADSP ADV SYNCS0 SYNCS1 WE7-WE0 Clock input Lower order address bits from processor Cache Controller Address Strobe input Processor Address Strobe input Burst Address Advance input 5V Supply
CYM74B550 CYM74P550A CYM74S550, CYM74S551
Description 3.3V Supply are CYM74P550A and CYM74S55X only Ground Addresses from processor 64-bit Data bus from processor Even bank output enable input 8-bit Tag RAM bidirectional bus Tag RAM write enable input 1-bit Dirty RAM input 1-bit Dirty RAM output Dirty RAM write enable input Presence Detect pins Signal not connected on module. Description Address Latch Enable input to transparent address latches Address bit A3 in async cache module (CYM74B550) Address bit A4 in async cache module (CYM74B550) Data RAM Chip Select inputs Even bank write enable input Description
Even bank synchronous burst RAM chip select input Odd bank synchronous burst RAM chip select input (not used) Write enable inputs to Data RAMs
Presence Detect Pins
PD3 Asynchronous - CYM74B550 Sync Pipelined - CYM74P550A Synch Burst - CYM74S550 Synch Burst - CYM74S551 NC NC NC NC PD2 NC NC NC GND PD1 GND GND NC NC PD0 GND NC GND GND
5
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -55C to +125C Ambient Temperature with Power Applied ......................................... -0C to +70C 3.3V Supply Voltage to Ground Potential....... -0.5V to +4.6V 5V Supply Voltage to Ground Potential.......... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +4.6V
CYM74B550 CYM74P550A CYM74S550, CYM74S551
DC Input Voltage ............................................-0.5V to +4.6V Output Current into Outputs (LOW)............................. 20 mA
Operating Range
Range Commercial (CYM74B550) Commercial (CYM74P550A, CYM74S55X) Ambient Temperature 0C to +70C 0C to +70C VCC5 5V 5% 5V 5% VCC3 N/A 3.3V +10%- 5%
Electrical Characteristics Over the Operating Range
Parameter VIH VIL VIL VOH VOL ICC (74B550) ICC (74P550A) ICC (74S550) ICC (74S551) Description Input HIGH Voltage Input LOW Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Operating Supply Current Operating Supply Current Operating Supply Current Operating Supply Current CYM74B550 CYM74P550A, CYM74S55X VCC3=Min. IOH = -4 mA VCC3=Min. IOL = 8 mA VCC5=Max., IOUT=0 mA, f=fMAX VCC5=Max.,VCC3=Max., IOUT=0 mA, f=fMAX VCC5=Max., VCC3=Max., IOUT=0 mA, f=fMAX VCC5=Max., VCC3=Max., IOUT=0 mA, f=fMAX Test Condition Min. 2.2 -0.5 -0.3 2.4 0.4 1650 900 1500 1500 0.8 0.8 Max. Unit V V V V V mA mA mA mA
Ordering Information
Speed (MHz) 50 Ordering Code CYM74B550PM-50C CYM74P550APM-50C CYM74S550PM-50C CYM74S551PM-50C 60 CYM74B550PM-60C CYM74P550APM-60C CYM74S550PM-60C CYM74S551PM-60C 66 CYM74B550PM-66C CYM74P550APM-66C CYM74S550PM-66C CYM74S551PM-66C Document #: 38-M-00076-A PM35 PM42 PM33 PM33 160-Pin Dual-Readout SIMM PM35 PM42 PM33 160-Pin Dual-Readout SIMM Package Name PM35 PM42 PM33 Package Type 160-Pin Dual-Readout SIMM Description Async 256 KB Sync Pipelined 256 KB Sync Burst 256 KB Sync Burst 512 KB Async 256 KB Sync Pipelined 256 KB Sync Burst 256 KB Sync Burst 512 KB Async 256 KB Sync Pipelined 256 KB Sync Burst 256 KB Sync Burst 512 KB Commercial Commercial Operating Range Commercial
6
PRELIMINARY
Package Diagrams
CYM74B550 CYM74P550A CYM74S550, CYM74S551
160-Pin Dual Readout SIMM (PM35)
160-Pin Dual Readout SIMM (PM33)
7
PRELIMINARY
Package Diagrams (continued)
CYM74B550 CYM74P550A CYM74S550, CYM74S551
160-Pin Dual Readout SIMM (PM42)
(c) Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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